Equivalence checking and intersection of deterministic timed finite state machines

Abstract There has been a growing interest in defining models of automata enriched with time, such as finite extended clocks (timed automata). In this paper, we study deterministic timed state machines (TFSMs), i.e., single clock, guards and timeouts which transduce input words into output words. We solve the problem equivalence checking by bisimulation from FSMs to untimed ones vice versa. Moreover, apply these relations build intersection two untiming them, intersecting them transforming back intersection. It is known that many problems like inclusion are undecidable for automata. Our results show TFSMs correspond decidable subclass admits restricted form $$\varepsilon $$ ε -transitions (i.e., timeouts) where most relevant decidable.